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19-3099; Rev 0; 12/07
Dual-Output Buck Controller with Tracking/Sequencing
General Description
The MAX15002 is a dual-output, pulse-width-modulated (PWM), step-down DC-DC controller with tracking and sequencing options. The device operates over the input voltage range of 5.5V to 23V or 5V 10%. Each PWM controller provides an adjustable output down to 0.6V and delivers at least 15A of load current with excellent load and line regulation. The MAX15002 is optimized for highperformance, small-size power management solutions. The options of Coincident Tracking, Ratiometric Tracking, and Output Sequencing allow the tailoring of the power-up/power-down sequence depending on the system requirements. Each of the MAX15002 PWM sections utilizes a voltage-mode control scheme with external compensation, allowing for good noise immunity and maximum flexibility with a wide selection of inductor values and capacitor types. Each PWM section operates at the same, fixed switching frequency that is programmable from 200kHz to 2.2MHz and can be synchronized to an external clock signal using the SYNC input. Each converter operating at up to 2.2MHz with 180 out-of-phase, increases the input capacitor ripple frequency up to 4.4MHz, thereby significantly reducing the RMS input ripple current and the size of the input bypass capacitor requirement. The MAX15002 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converter. The poweron reset (RESET) with an adjustable timeout period monitors both outputs and provides a RESET signal to the processor when both outputs are within regulation. Protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. The MAX15002 is available in a space-saving, 6mm x 6mm, 40-pin TQFN-EP package and is specified for operation over the -40C to +125C automotive temperature range. See the MAX15003 data sheet for a triple version of the MAX15002.
Features
o 5.5V to 23V or 5V 10% Input Voltage Range o Dual-Output Synchronous Buck Controller o Selectable In-Phase or 180 Out-of-Phase Operation o Output Voltages Adjustable from 0.6V to 0.85VIN o Lossless Valley-Mode Current Sensing or Accurate Valley Current Sensing Using RSENSE o External Compensation for Maximum Flexibility o Digital Soft-Start and Soft-Stop o Sequencing or Coincident/Ratiometric VOUT Tracking o Individual PGOOD Outputs o RESET Output with a Programmable Timeout Period o 200kHz to 2.2MHz Programmable Switching Frequency o External Frequency Synchronization o Hiccup Mode Short-Circuit Protection o Space-Saving (6mm x 6mm) 40-Pin TQFN Package
MAX15002
Ordering Information
PART MAX15002ATL+ TEMP RANGE -40C to +125C PINPACKAGE 40 TQFN-EP* (6mm x 6mm) PKG CODE T4066-3
+Denotes a lead-free package.
Applications
PCI Express(R) Host Bus Adapter Power Supplies Networking/Server Power Supplies Point-of-Load DC-DC Converters
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
PCI Express is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
ABSOLUTE MAXIMUM RATINGS
IN, LX_, CSN_ to SGND..........................................-0.3V to +30V BST_ to SGND ........................................................-0.3V to +30V BST_ to LX_ ..............................................................-0.3V to +6V REG, DREG_, SYNC, EN_, RT, CT, RESET, PHASE, SEL to SGND ...............................-0.3V to +6V ILIM_, PGOOD_, FB_, COMP_, CSP_ to SGND .......-0.3V to +6V DL_ to PGND_.......................................-0.3V to (VDREG_ + 0.3V) DH_ to LX_ ...............................................-0.3V to (VBST_ + 0.3V) PGND_ to SGND, PGND_ to Any Other PGND_.......-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 40-Pin TQFN (derate 37mW/C above +70C) .............2963mW* JA ..................................................................................27C/W Jc .................................................................................1.4C/W Operating Junction Temperature Range ...........-40oC to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C *As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2F, RRT = 100k, CCT = 0.1F, RILIM_ = 60k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25C.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS Input-Voltage Range Input Undervoltage Lockout Threshold Input Undervoltage Lockout Hysteresis Operating Supply Current Shutdown Supply Current REG VOLTAGE REGULATOR Output-Voltage Setpoint Load Regulation DIGITAL SOFT-START/SOFT-STOP Soft-Start/Soft-Stop Duration Reference Voltage Steps ERROR TRANSCONDUCTANCE AMPLIFIER FB_, TRACK_ Input Bias Current FB_ Voltage Setpoint FB_ to COMP_ Transconductance COMP_ Output Swing Open-Loop Gain Unity-Gain Bandwidth 0.75 80 10 VFB TA = TJ = 0C to +85C TA = TJ = -40C to +125C -250 0.593 0.590 0.600 0.600 2.1 3.50 +250 0.605 0.608 nA V V mS V dB MHz 2048 64 Clocks Steps VREG VIN = 5.5V to 23V IREG = 0 to 120mA, VIN = 12V 4.9 5.2 0.2 V V VIN = 12V, VFB_ = 0.8V VIN = 12V, EN_ = 0V, PGOOD_ unconnected VIN VUVLO 5.5 VIN = VREG = VDREG (Note 2) VIN rising 4.5 3.95 4.05 0.35 4.3 150 6.0 300 23.0 5.5 4.15 V V V V mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual-Output Buck Controller with Tracking/Sequencing
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2F, RRT = 100k, CCT = 0.1F, RILIM_ = 60k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25C.) (Note 1)
PARAMETER DRIVERS DL_, DH_ Break-Before-Make Time DH1 On-Resistance DH2 On-Resistance DL1 On-Resistance DL2 On-Resistance LX_ to PGND_ On-Resistance CURRENT-LIMIT AND HICCUP MODE Cycle-By-Cycle Valley CurrentLimit Adjustment Range Cycle-By-Cycle Valley CurrentLimit Threshold Tolerance ILIM_ Reference Current ILIM_ Reference Current Temperature Coefficient CSP_, CSN_ Input Bias Current Number of Cumulative CurrentLimit Events to Hiccup Number of Consecutive NonCurrent-Limit Cycles to Clear NCL Hiccup Timeout ENABLE/PHASE/SEL EN1 Threshold EN1 Threshold Hysteresis EN1 Input Bias Current PHASE Input High PHASE Input Low PHASE Input Bias Current SEL Threshold SEL Input Bias Current -1 -1 -1 2 0.8 +1 20 +1 VEN-TH EN1 rising 1.19 1.215 0.12 +1 1.24 V V A V V A %VREG A NCL NCLR VCSP_ = 0V, VCSN_ = -0.3V -20 8 3 4096 Clock periods VCL VCL_ = VILIM_/10 VILIM_ = 0.5V VILIM_ = 3V VILIM_ = 0 to 3V, TA = TJ = +25C 50 44 288 20 3333 +20 300 54 312 mV mV A ppm/C A CLOAD = 5nF Low, sinking 100mA High, sourcing 100mA Low, sinking 100mA High, sourcing 100mA Low, sinking 100mA High, sourcing 100mA Low, sinking 100mA High, sourcing 100mA Sinking 10mA 20 0.9 1.3 0.9 1.3 0.9 1.3 0.9 1.3 8 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX15002
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3
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2F, RRT = 100k, CCT = 0.1F, RILIM_ = 60k, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25C.) (Note 1)
PARAMETER PGOOD, RESET OUTPUTS FB_ for PGOOD Threshold RESET, PGOOD_ Output Low Level RESET, PGOOD_ Leakage CT Charging Current CT Output Low CT Threshold for RESET Delay OSCILLATOR Switching Frequency Range (Each Converter) Switching Frequency Accuracy (Each Converter) Phase Delay RT Voltage Minimum Controllable On-Time Minimum Off-Time SYNC High-Level Voltage SYNC Low-Level Voltage SYNC Internal Pulldown Resistor SYNC Frequency Range SYNC Minimum On-Time SYNC Minimum Off-Time PWM Ramp Amplitude (Peak-Peak) PWM Ramp Valley (Note 3) 50 0.4 30 30 2 1 100 VRT tON(MIN) tOFF(MIN) 2 0.8 200 4.6 fSW VSYNC = 0V, fSW = 1.5 x 1011/RRT + 2k fSW 1500kHz fSW > 1500kHz VPHASE = 0V (DH1 rising to DH2 rising) VPHASE = VREG (DH1 rising to DH2 rising) 40k < RRT < 500k 200 -5 -7 180 0 2 75 150 2200 +5 +7 kHz % degrees degrees V ns ns V V k MHz ns ns V V Sinking 3mA CT rising CT falling 1.8 1.2 FB_ falling Sinking 3mA -1 1.8 2 0.54 0.555 0.57 0.1 +1 2.2 0.1 2.6 V V A A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: 100% production tested at TA = TJ = +25C and TA = TJ = +125C. Limits at other temperatures are guaranteed by design. Note 2: For 5V applications, connect REG directly to IN. Note 3: The switching frequency is 1/2 of the SYNC frequency.
4
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Dual-Output Buck Controller with Tracking/Sequencing
Typical Operating Characteristics
(VIN = 12V, referenced to Figure 8, TA = TJ = +25C, unless otherwise noted.)
MAX15002
CONVERTER 1 EFFICIENCY vs. LOAD CURRENT
MAX15002 toc01
CONVERTER 2 EFFICIENCY vs. LOAD CURRENT
MAX15002 toc02
CONVERTER 1 LOAD REGULATION
VOUT1 = 3.3V OUTPUT-VOLTAGE ACCURACY (%) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 100 0 5 10 15
MAX15002 toc03
100 90 EFFICIENCY (%) 80 70 60 50 40 0.1 1 10 LOAD CURRENT (A) VIN = 6V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 VIN = 12V VIN = 16V VIN = 6V
1.00
VIN = 12V VIN = 16V
VOUT1 = 3.3V fSW = 300kHz 100
10 0 0.1 1 10 LOAD CURRENT (A)
VOUT2 = 1.8V fSW = 300kHz
LOAD CURRENT (A)
CONVERTER 2 LOAD REGULATION
MAX15002 toc04
INTERNAL VOLTAGE REGULATION (REG)
4.99 4.98 4.97
MAX15002 toc05
CONVERTER-SWITCHING FREQUENCY vs. RRT
MAX15002 toc06
1.00 OUTPUT-VOLTAGE ACCURACY (%) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 5 10 VOUT2 = 1.8V
5.00
10,000
SWITCHING FREQUENCY (kHz)
1000
VREG (V)
4.96 4.95 4.94 4.93 4.92 4.91 4.90 VIN = 12V CREG = 2.2F
100
10 0 20 40 60 80 100 0 200 400 RRT (k) 600 800 TEMPERATURE (C)
15
LOAD CURRENT (A)
SWITCHING FREQUENCY ACCURACY vs. TEMPERATURE
MAX15002 toc07
VALLEY CURRENT-LIMIT THRESHOLD vs. VILIM
VALLEY CURRENT-LIMIT THRESHOLD (mV)
MAX15002 toc08
10 SWITCHING FREQUENCY ACCURACY (%) 8 6 4 2 0 -2 -4 -6 -8 -10 -50 -25 0 25 50 75 fSW = 300kHz
350 300 250 200 150 100 50
100 125 150
500
1000
1500
2000 VILIM (mV)
2500
3000
3500
TEMPERATURE (C)
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5
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25C, unless otherwise noted.)
VALLEY CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
MAX15002 toc09
SWITCHING CURRENT vs. FREQUENCY
14 SWITCHING CURRENT (mA) 13 12 11 10 9 8 7 VIN = 12V DL_, DH_ UNCONNECTED VFB_ = 0V 200 700 1200 FREQUENCY (kHz) 1700 2200
MAX15002 toc10
RATIOMETRIC STARTUP
MAX15002 toc11
100 VALLEY CURRENT-LIMIT THRESHOLD (mV) RILIMc = 25.5k 90 80 70 60 50 40 30 TEMP COEFFICIENT (nom.) = 3,333ppm/C 20 -50 -25 0 25 50 75
15
10V/div VIN 0V
1V/div
1V/div
6 5
VOUT1, 2
0V VEN2 = 0V, SEL = REG 2ms/div
100 125 150
TEMPERATURE (C)
RATIOMETRIC SHUTDOWN
MAX15002 toc12
CHANNEL 2 SHORT CIRCUIT (RATIOMETRIC MODE)
MAX15002 toc13
CHANNEL 1 SHORT CIRCUIT (RATIOMETRIC MODE)
MAX15002 toc14
VOUT2
VIN 500mV/div V OUT2
10V/div 0V 1V/div 0V
VIN VOUT1
10V/div 0V 2V/div 0V
VOUT1
500mV/div VOUT1 2V/div 0V VEN2 = 0V, SEL = REG 1ms/div VEN2 = 0V, SEL = REG 1ms/div 0V
VOUT2 1V/div 0V VEN2 = 0V, SEL = REG 1ms/div
COINCIDENT STARTUP
MAX15002 toc15
COINCIDENT SHUTDOWN
MAX15002 toc16
VOUT1 10V/div VIN 0V 500mV/div VOUT2
1V/div
1V/div VOUT1, 2 CIRCUIT OF FIGURE 8, SEL = REG 2ms/div 2ms/div
500mV/div
0V
0V
6
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Dual-Output Buck Controller with Tracking/Sequencing
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25C, unless otherwise noted.)
MAX15002
CHANNEL 2 SHORT CIRCUIT (COINCIDENT MODE)
MAX15002 toc17
CHANNEL 1 SHORT CIRCUIT (COINCIDENT MODE)
MAX15002 toc18
SEQUENCING STARTUP
MAX15002 toc19
VIN VOUT2
10V/div 0V 1V/div 0V
VIN
10V/div VIN
10V/div 0V
VOUT1
0V 2V/div 0V 1V/div
VOUT1 2V/div 0V
VOUT2 1V/div 0V VOUT1, 2 SEL = REG 1ms/div 1ms/div 4ms/div
1V/div
0V
SEQUENCING SHUTDOWN
MAX15002 toc20
CONVERTER 2 OUTPUT SHORT CIRCUIT (SEQUENCING MODE)
MAX15002 toc21
CHANNEL 1 OUTPUT SHORT CIRCUIT (SEQUENCING MODE)
MAX15002 toc22
VOUT1
VIN 500mV/div V OUT2
10V/div 0V 1V/div
VIN VOUT1
10V/div 0V 2V/div 0V
VOUT2 500mV/div VOUT1 0V SEL = REG 1ms/div
0V 2V/div VOUT2
1V/div SEL = GND EN/TRACK2 = PGOOD1 1ms/div 0V SEL = GND EN/TRACK2 = PGOOD1 1ms/div 0V
RESET AT STARTUP (SEQUENCING MODE)
MAX15002 toc23
RESET AT SHUTDOWN (SEQUENCING MODE)
MAX15002 toc24
5V/div VRESET 0V
VRESET
5V/div 0V
1V/div 1V/div
VOUT1 1V/div 1V/div
VOUT2
VOUT1, 2
SEL = GND EN/TRACK2 = PGOOD1 20ms/div
0V
SEL = GND EN/TRACK2 = PGOOD1 1ms/div
0V
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7
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25C, unless otherwise noted.)
CONVERTER 1 SHORT-CIRCUIT CONDITION (HICCUP MODE)
MAX15002 toc25
180 OUT-OF-PHASE OPERATION
MAX15002 toc26
VOUT1
500mV/div VSYNC
5V/div 0V 10V/div
IOUT1
10A/div VLX1
0V
VLX1 VDL1 VPGOOD1
10V/div 5V/div 1V/div VLX2 10V/div 0V
4ms/div
1s/div
IN-PHASE OPERATION
MAX15002 toc27
BREAK-BEFORE-MAKE TIMING
MAX15002 toc28
VLX1 VSYNC 5V/div 0V 10V/div 0V VDL1 10V/div 0V
5V/div
0V
VLX1
2V/div
VLX2
0V 20ns/div
1s/div
LOAD-TRANSIENT RESPONSE (IOUT2 = 100mA TO 10A)
MAX15002 toc29
LOAD-TRANSIENT RESPONSE (IOUT2 = 5A TO 10A)
MAX15002 toc30
VOUT2
100mV/div AC-COUPLED VOUT2
100mV/div AC-COUPLED
IOUT2 5A/div 0 200s/div
IOUT2
5A/div
0 200s/div
8
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Dual-Output Buck Controller with Tracking/Sequencing
Pin Description
PIN 1 2 NAME REG SEL FUNCTION 5V Regulator Output. Bypass with a 2.2F ceramic capacitor to SGND. Track/Sequence Select Input. At startup, connect SEL to REG to configure as a dual tracker or connect SEL to SGND to configure as a dual sequencer. Note: When configured as a dual sequencer, each rail is independently controlled by EN_. Controller 1 Power-Ground Connection. Connect the input filter capacitor's negative terminal, the source of the synchronous MOSFET, and the output filter capacitor's return to PGND1. Connect externally to SGND at a single point near the input capacitor return terminal. Controller 1 Low-Side Gate Driver Output. DL1 is the gate driver output for the synchronous MOSFET. Controller 1 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode. Connect a minimum of 0.1F ceramic capacitor from DREG1 to PGND1. Controller 1 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the inductor and the negative side of the boost capacitor to LX1. Controller 1 High-Side Gate Driver Output. DH1 drives the gate of the high-side MOSFET. Controller 1 High-Side Gate Driver Supply. Connect BST1 to the cathode of the boost diode and to the positive terminal of the boost capacitor. Controller 1 Negative Current-Sense Input. Connect CSN1 to the synchronous MOSFET drain (connected to LX1). When using a current-sense resistor, connect CSN1 to the junction of a low-side MOSFET's source and the current-sense resistor. See Figure 10. Controller 1 Positive Current-Sense Input. Connect CSP1 to the synchronous MOSFET source (connected to PGND1). When using a current-sense resistor, connect CSP1 to the PGND1 end of the current-sense resistor. Controller 1 Valley Current-Limit Set Output. Connect a 25k to 150k resistor, RILIM1, from ILIM1 to SGND to program the valley current-limit threshold from 50mV to 300mV. ILIM1 sources 20A out to RILIM1. The resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense resistor, connect a resistive divider from REG to ILIM1 to SGND to set the valley current limit. See Figure 10. Controller1 Error Transconductance Amplifier Output. Connect COMP1 to the compensation feedback network. Controller 1 Enable Input. EN1 must be above 1.24V, VEN-TH, for the PWM controller to start Output 1. Controller 1 is the master. Use the master as the highest output voltage in a coincident tracking configuration. Controller 1 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to SGND to set the output voltage. The FB1 voltage regulates to VFB (0.6V). Controller 1 Power-Good Output. Open-drain PGOOD1 output goes high impedance (releases) when FB1 is above 0.925 x VFB (0.555V). Controller 2 Power Ground Connection. Connect the input filter capacitor's negative terminal, the source of the synchronous MOSFET, and the output filter capacitor's return to PGND2. Connect externally to SGND at a single point near the input capacitor return terminal. Controller 2 Low-Side Gate Driver Output. DL2 is the gate driver output for the synchronous MOSFET. Controller 2 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode. Connect a minimum of a 0.1F ceramic capacitor from DREG2 to PGND2. Controller 2 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the inductor and the negative side of the boost capacitor to LX2.
MAX15002
3 4 5 6 7 8
PGND1 DL1 DREG1 LX1 DH1 BST1
9
CSN1
10
CSP1
11
ILIM1
12
COMP1
13
EN1
14 15
FB1 PGOOD1
16 17 18 19
PGND2 DL2 DREG2 LX2
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9
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Pin Description (continued)
PIN 20 21 NAME DH2 BST2 FUNCTION Controller 2 High-Side Gate Driver Output. DH2 drives the gate of the high-side MOSFET. Controller 2 High-Side Gate Driver Supply. Connect BST2 to the cathode of the boost diode and to the positive terminal of the boost capacitor. Controller 2 Negative Current-Sense Input. Connect CSN2 to the synchronous MOSFET drain (connected to LX2). When using a current-sense resistor, connect CSN2 to the junction of the low-side MOSFET's source and the current-sense resistor. See Figure 10. Controller 2 Positive Current-Sense Input. Connect CSP2 to the synchronous MOSFET source (connected to PGND2). When using a current-sense resistor, connect CSP2 to the PGND2 end of the current-sense resistor. Controller 2 Valley Current-Limit Set Output. Connect a 25k to 150k resistor, RILIM2, from ILIM2 to SGND to program the valley current-limit threshold from 50mV to 300mV. ILIM2 sources 20A out to RILIM2. The resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense resistor, connect a resistive divider from REG to ILIM2 to SGND to set the valley current limit. See Figure 10. Controller 2 Error Transconductance Amplifier Output. Connect COMP2 to the compensation feedback network. Controller 2 Enable/Tracking Input. See Figure 2. When sequencing, EN/TRACK2 must be above 1.24V for the PWM controller 2 to start. Coincident tracking--connect the same resistive divider used for FB2, from Output 1 to EN/TRACK2 to SGND. Ratiometric tracking--connect EN/TRACK2 to analog ground. Controller 2 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to SGND to set the output voltage. The FB2 voltage regulates to VFB (0.6V). Controller 2 Power-Good Output. Open-drain PGOOD2 output goes high impedance (releases) when FB2 is above 0.925 x VFB (0.555V). No Connection. Not internally connected. Synchronization Input. Drive with a frequency at least 20% higher than two times the frequency programmed using the RT pin. The switching frequency is 1/2 the SYNC frequency. Connect SYNC to SGND when not used. Analog Ground Connection. Connect SGND and PGND_ together at one point near the input bypass capacitor return terminal. Oscillator Timing Resistor Connection. Connect a 750k to 68k resistor from RT to SGND to program the switching frequency from 200kHz to 2.2MHz. Phase Select Input. Connect PHASE to SGND for 180 out-of-phase operation between the controllers. Connect to REG for in phase operation. RESET Output. Open-drain RESET output releases after all PGOODs are released and timeout programmed by CT finishes. RESET Timeout Capacitor Connection. Connect a timing capacitor from CT to analog ground to set the RESET delay. CT sources 2A into the timing capacitor. When the voltage at CT passes 2V, open-drain RESET goes high impedance. Supply Input Connection. Connect to an external voltage source from 5.5V to 23V. For 4.5V to 5.5V input application, connect IN and REG together. Exposed Pad. Solder the exposed pad to a large SGND plane.
22
CSN2
23
CSP2
24
ILIM2
25
COMP2
26
EN/TRACK2
27 28 29-33 34
FB2 PGOOD2 N.C. SYNC
35 36 37 38
SGND RT PHASE RESET
39
CT
40 --
IN EP
10
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Dual-Output Buck Controller with Tracking/Sequencing
Functional Diagrams
PWM CONTROLLER 1
IN SEL EN1 CT RESET
MAX15002
LDO REG EN 1.24V 1.12V
CONFIG SELECTOR
1.24VON 1.12VOFF
RESET TIMEOUT
MAX15002
SEQ_ PGPD_ SGND
SHDN 0.6V REF VREF DOWN1 VREGOK EN1 OVL CONFIG RES OVERLOAD MANAGEMENT OVL_ CURRENTLIMIT SET CLK1 SEQ_
CSP1
CSN1
DIGITAL SOFT-START AND STOP CLK1 FB1
ILIM1
VR1 E/A
OVL1 IMAX1
BST1 DH1
R COMP1 SYNC RT PHASE EN OSC RAMP LEVEL CLK1 SHIFT 0.925 x VREF FB1 CPWM
Q
LX1
SET DOMINANT S
DREG1 DL1 PGND1
CLK2
PGPD1
PGOOD1
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11
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Functional Diagrams (continued)
PWM CONTROLLER 2
EN/TRACK2
MAX15002
SEQ_ VREF DOWN2 CLK2 SEL_ VREF VR2 E/A EN CONFIG EN1 SHDN EN2
1.24VON 1.12VOFF SEQ_
CSP2
CSN2 OVL CONFIG OVL_ CURRENTLIMIT SET CLK2 ILIM2
DIGITAL SOFT-START AND STOP EN/ TRACK2 FB2
OVL2 RES OVERLOAD IMAX2 MANAGEMENT
BST2 DH2
R COMP2 CPWM CLK2 RAMP LEVEL SHIFT CLK2 0.925 x VREF FB2
Q
LX2 DREG2 DL2 PGND2
SET DOMINANT S
PGPD2
PGOOD2
Detailed Description
The MAX15002 is a dual-output, pulse-width-modulated (PWM), step-down, DC-DC controller with tracking and sequencing options. The device operates over the input voltage range of 5.5V to 23V or 5V 10%. Each PWM controller provides an adjustable output down to 0.6V and delivers at least 15A of load current with excellent load and line regulation. Each of the MAX15002 PWM sections utilizes a voltage-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 200kHz to 2.2MHz and can be synchronized to an external clock signal using the SYNC input. Each converter, operating at up to 2.2MHz with 180 out-of-phase, increases the input capacitor ripple frequency up to 4.4MHz, reducing the RMS input ripple current and the size of the input bypass capacitor requirement significantly.
The MAX15002 provides Coincident Tracking, Ratiometric Tracking, and Sequencing. This allows tailoring of the power-up/power-down sequence depending on the system requirements. The MAX15002 features lossless valley-mode currentlimit protection by monitoring the voltage drop across the synchronous MOSFET's on-resistance to sense the inductor current. The MAX15002's internal current source exhibits a positive temperature coefficient to help compensate for the MOSFET's temperature coefficient. Use an external voltage-divider when a more precise current limit is desired. This divider along with a precision shunt resistor allows for more accurate current limit. The MAX15002 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converter. The power-on reset (RESET) with adjustable timeout period monitors both outputs and provides a RESET signal to the processor indicating when the outputs are within regulation. Protection features include lossless valleymode current limit and hiccup mode output short-circuit protection.
12
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Dual-Output Buck Controller with Tracking/Sequencing
Internal Undervoltage Lockout (UVLO)
VIN must exceed the default UVLO threshold before any operation can commence. The UVLO circuitry keeps the MOSFET drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. The UVLO rising threshold is 4.05V with 350mV hysteresis. an RC filter (1 to 3.3 and 2.2F//0.1F ceramic capacitors are typical) from REG to DREG_ filters out high-peak currents. Alternatively, DREG can be connected to an external source (VDREG-EXT). Note that the DREG voltage should be high enough to fully enhance the low-side MOSFET. To avoid partial enhancing of the MOSFETs, use the VDREG-EXT to set the UVLO externally using EN1. BST_ supplies the power for the high-side MOSFET drivers. Connect the bootstrap diode from BST_ to DREG_ (anode at DREG_ and cathode at BST_). Connect a bootstrap 0.1F or higher ceramic capacitor between BST_ and LX_. Though not always necessary, it may be useful to insert a small resistor (4.7 to 22) in series with the BST_ pin and the cathode of the bootstrap diode for additional noise immunity. The high-side (DH_) and low-side (DL_) drivers drive the gates of the external n-channel MOSFETs. The drivers' 2A peak source- and sink-current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced switching losses. The gate driver circuitry also provides a break-beforemake time (20ns typ) to prevent shoot-through currents during transition.
MAX15002
Digital Soft-Start/Soft-Stop
The MAX15002 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating outputvoltage overshoot. Soft-start begins after VIN exceeds the undervoltage lockout threshold and the enable input is above 1.24V. The soft-start circuitry gradually ramps up the reference voltage. This controls the rate of rise of the output voltage and reduces input surge currents during startup. The soft-start duration is 2048 clock cycles. The output voltage is incremented through 64 equal steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load. Soft-stop commences when the enable input falls below 1.12V. The soft-stop circuitry ramps down the reference voltage controlling the output voltage rate of fall. The output voltage is decremented through 64 equal steps in 2048 clock cycles.
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO powered from IN which provides power to the IC. Connect REG externally to DREG to provide power for the low-side MOSFET gate driver. Bypass REG to SGND with a minimum 2.2F ceramic capacitor. Place the capacitor physically close to the MAX15002 to provide good bypassing. REG is intended for powering only the internal circuitry and should not be used to supply power to external loads. REG can source up to 120mA. This current, I REG , includes quiescent current (IQ) and gate drive current (IDREG): IREG = IQ + [fSW x (QGHS_ + QGLS_)] where QGHS_ + QGLS_ is the total gate charge of each of the respective high- and low-side external MOSFETs at VGATE = 5V. fSW is the switching frequency of the converter and IQ is the quiescent current of the device at the switching frequency.
Oscillator/Synchronization Input/Phase Staggering (RT, SYNC, PHASE)
Use an external resistor at RT to program the MAX15002 switching frequency from 200kHz to 2.2MHz. Choose the appropriate resistor at RT to calculate the desired output switching frequency (fSW): fSW (Hz) = 1.5 x 1011/(RRT + 2000) Connect an external clock at SYNC for external clock synchronization. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by RRT. This maintains output regulation even with intermittent SYNC signals. For proper synchronization, the external frequency must be at least 20% higher than twice the frequency programmed through the RT input. The switching frequency is 1/2 the SYNC frequency. Connect SYNC to SGND when not used. Connect PHASE to SGND for 180 out-of-phase operation between the controllers. Connect PHASE to REG for in-phase operation.
MOSFET Gate Drivers
DREG_ is the supply input for the low-side MOSFET driver. Connect DREG_ to REG externally. Everytime the low-side MOSFET switches on, high peak current is drawn from DREG for a short amount of time. Adding
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Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Coincident/Ratiometric Tracking (SEL, EN/TRACK2)
The enable/tracking input in conjunction with digital soft-start and soft-stop provides coincident/ratiometric tracking. See Figure 1. Track an output voltage by connecting a resistive divider from the output being tracked to the enable/tracking input. For example, for VOUT2 to coincidentally track VOUT1, connect the same resistive divider used for FB2, from OUT1 to EN/TRACK2 to SGND. See Figure 2 and the Coincident Startup and Coincident Shutdown graphs in the Typical Operating Characteristics. Track ratiometrically by connecting EN/TRACK2 to SGND. This synchonizes the soft-start and soft-stop of all the controllers' references, and hence their respective output voltages will track ratiometrically. See Figure 2 and the Ratiometric Startup and Ratiometric Shutdown graphs in the Typical Operating Characteristics. Connect SEL to REG to configure as a dual tracker. When the MAX15002 converter is configured as a tracker, the output short-circuit fault situations at master or slave output is handled carefully so that either the master or slave output does not stay on when the other output is shorted to the ground. When the slave is shorted and enters in hiccup mode, the master will softstop. When the master is shorted and the part enters in hiccup mode, the slave will ratiometrically soft-stop. Coming out of the hiccup, all outputs will soft-start coincidently or ratiometrically depending on their initial configuration. See the Typical Operating Characteristics for the output behaviour during the fault conditions. During the thermal shutdown or power-off, when the input falls below its UVLO, the output voltages fall down at the rate depending on the respective output capacitor and load. See Figure 1.
SOFT-START VOUT1 VOUT2
SOFT-START
SOFT-STOP
A) COINCIDENT TRACKING OUTPUTS
VOUT1 VOUT2
SOFT-STOP
B) RATIOMETRIC TRACKING OUTPUTS
VOUT1 VOUT2
SOFTSTART
SOFT-STOP C) SEQUENCED OUTPUTS
Output-Voltage Sequencing (SEL, EN/TRACK2, PGOOD)
Referring to Figure 1c, when sequencing, the enable/tracking input must be above 1.24V for each PWM controller to start. The PGOOD_ outputs and EN/TRACK2 inputs can be daisy-chained to generate power sequencing. Open-drain PGOOD_ outputs go high impedance when FB_ is above the PGOOD_ threshold (555mV typ).
Figure 1. Graphical Representation of Coincident Tracking, Ratiometric Tracking, and PGOOD Sequencing
Connect the power-good output to the enable/tracking input to set when the other controller will start. See Figure 2. Connect SEL to SGND to configure as a dual sequencer.
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Dual-Output Buck Controller with Tracking/Sequencing MAX15002
RATIOMETRIC TRACKING VIN COINCIDENT TRACKING VIN PGOOD SEQUENCING VIN
EN1
EN1
EN1
VOUT1 EN/TRACK2 RA EN/TRACK2 SEL REG RB PGOOD1 EN/TRACK2 REG
VOUT2 RA FB2 RB
SEL
SEL
REG
Figure 2. Ratiometric Tracking, Coincident Tracking, PGOOD Sequencing Configurations
Error Amplifier
The output of the internal error transconductance amplifier (COMP_) is provided for frequency compensation (see the Compensation Design Guidelines section). The inverting input is FB_ and the output COMP_. The error transamplifier has an 80dB open-loop gain and a 10MHz GBW product.
Output Short-Circuit Protection (Hiccup Mode)
The current-limit circuit employs a valley current-limiting algorithm that either uses a shunt or the synchronous MOSFET's on-resistance as the current-sensing element. Once the high-side MOSFET turns off, the voltage across the current-sensing element is monitored. If this voltage does not exceed the current-limit threshold,
the high-side MOSFET turns on normally at the start of the next cycle. If the voltage exceeds the current-limit threshold just before the beginning of a new PWM cycle, the controller skips that cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to decrease because the on-time of the low-side MOSFET extends beyond a clock cycle. If the current-limit threshold is exceeded for more than eight cumulative clock cycles (NCL), the device shuts down (both DH and DL are pulled low) for 4096 clock cycles (hiccup timeout) and then restarts with a softstart sequence. If three consecutive cycles pass without a current-limit event, the count of NCL is cleared (see Figure 3). Hiccup mode protects against a continuous output short circuit.
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Dual-Output Buck Controller with Tracking/Sequencing MAX15002
INITIATE HICCUP TIMEOUT NHT
The minimum input voltage is limited by the maximum duty cycle and is calculated using the following equation: VIN(MIN)
CURRENT LIMIT
IN COUNT OF 8 NCL CLR
1 - t OFF(MIN) x fSW
(
VOUT
)
where tOFF(MIN) typically is equal to 150ns.
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX15002: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IP-P). Higher IP-P allows for a lower inductor value. A lower inductance value minimizes size and cost and improves large-signal and transient response. However, efficiency is reduced due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. A higher inductance increases efficiency by reducing the ripple current, however resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good rule of thumb is to choose IP-P equal to 30% of the full load current. Calculate the inductance using the following equation:
L=
IN COUNT OF 3 NCLR CLR
Figure 3. Hiccup-Mode Block Diagram
PWM Controller Design Procedures
Setting the Switching Frequency
Connect a 750k to 68k resistor from RT to SGND to program the switching frequency from 200kHz to 2.2MHz. Calculate the switching frequency using the following equation: fSW (Hz) = 1.5 x 1011/(RRT + 2000) Higher frequencies allow designs with lower inductor values and less output capacitance. Consequently, peak currents and I 2 R losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase.
VOUT (VIN - VOUT ) VIN x fSW x IP -P
Effective Input Voltage Range
Although the MAX15002 converters can operate from input supplies ranging from 5.5V to 23V, the input voltage range can be effectively limited by the MAX15002 duty-cycle limitations for a given output voltage. The maximum input voltage is limited by the minimum ontime (tON(MIN)): VIN(MAX) where tON(MIN) is 75ns. VOUT t ON(MIN) x fSW
VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency is programmable between 200kHz and 2.2MHz (see Oscillator/Synchronization Input/Phase Staggering (RT, SYNC, PHASE) section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output current ripple is acceptable. The inductor saturation current (ISAT) is also important to avoid runaway current during continuous output short-circuit conditions. Select an inductor with an ISAT specification higher than the maximum peak current.
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Dual-Output Buck Controller with Tracking/Sequencing
Input Capacitor Selection
The discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage ripple within design requirements. The 180 ripple phase operation increases the frequency of the input capacitor ripple current to twice the individual converter switching frequency. When using ripple phasing, the worst-case input capacitor ripple current is when the one converter with the highest output current is on. The input voltage ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of VQ and VESR that peaks at the end of the on-cycle. Calculate the input capacitance and ESR required for a specified ripple using the following equations: VESR ESR = IP -P ILOAD(MAX) + 2 V ILOAD(MAX) x OUT VIN CIN = VQ x fSW where: IP -P = output ripple is mainly composed of VQ (caused by the capacitor discharge) and VESR (caused by the voltage drop across the equivalent series resistance of the output capacitor). The equations for calculating the output capacitance and its ESR are: COUT =
ESR =
MAX15002
IP -P 8 x VQ x fSW
2 x VESR IP -P
(VIN - VOUT ) x VOUT
VIN x fSW x L
ILOAD(MAX) is the maximum output current, IP-P is the peak-to-peak inductor current, and fSW is the switching frequency. For the condition with only one converter on, calculate the input ripple current using the following equation: ICIN(RMS) = ILOAD _ MAX x VOUT x (VIN - VOUT ) VIN
VESR and VQ are not directly additive because they are out of phase from each other. If using ceramic capacitors, which generally have low ESR, VQ dominates. If using electrolytic capacitors, VESR dominates. The allowable deviation of the output voltage during fast load transients also affects the output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the gain bandwidth of the converter (see the Compensation Design Guidelines section). The resistive drop across the output capacitor's ESR, the drop across the capacitor's ESL, and the capacitor discharge cause a voltage droop during the load-step (ISTEP). Use a combination of low-ESR tantalum/aluminum electrolyte and ceramic capacitors for better load-transient and voltage-ripple performance. Nonleaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: VESR ISTEP xt I COUT = STEP RESPONSE VQ
ESR = ESL =
The MAX15002 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. At lower input voltage, additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during transient loading.
VESL x t STEP ISTEP
Output Capacitor Selection
The allowed output voltage ripple and the maximum deviation of the output voltage during load steps determine the required output capacitance and its ESR. The
where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller.
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Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Setting the Current Limit
Connect a 25k to 150k resistor, RILIM, from ILIM to SGND to program the valley current-limit threshold (VCL) from 50mV to 300mV. ILIM sources 20A out to RILIM. The resulting voltage divided by 10 is the valley current-limit threshold. The MAX15002 uses a valley current-sense method for current limiting. The voltage drop across the low-side MOSFET due to its on-resistance is used to sense the inductor current. The voltage drop (VVALLEY) across the low-side MOSFET at the valley point and at ILOAD is: I VVALLEY = RDS(ON) x ILOAD - P -P 2 RDS(ON) is the on-resistance of the low-side MOSFET, ILOAD is the rated load current, and IP-P is the peakto-peak inductor current. The RDS(ON) of the MOSFET varies with temperature. Calculate the RDS(ON) of the MOSFET at its operating junction temperature at full load using the MOSFET datasheet. To compensate for this temperature variation, the 20A ILIM reference current has a temperature coefficient of 3333ppm/C. This allows the valley current-limit threshold (VCL) to track and partially compensate for the increase in the synchronous MOSFET's RDS(ON) with increasing temperature. Use the following equation to calculate RILIM:
I RDS(ON) x ICL(MAX) - P -P x10 2 RILIM = 20 x10 -6 1+ 3.333 x10 -3 (T - 25C) VALLEY CURRENT-LIMIT THRESHOLD AND RDS(ON) vs. TEMPERATURE
1.4 VILIM AND RDS(ON) (NORMALIZED) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (C) RILIM = 25.5k VILIM RDS(ON)
MAX15002 fig04
1.5
Figure 4. Current-Limit Trip Point and VRDS(ON) vs. Temperature
Compensation Design Guidelines
The MAX15002 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by differentially comparing the output voltage against a fixed reference. The subsequent error voltage that appears at the error amplifier output (COMP) is compared against an internal ramp voltage to generate the required duty cycle of the pulse-width modulator. A second order lowpass LC filter removes the switching harmonics and passes the DC component of the pulse-width-modulated signal to the output. The LC filter, which has an attenuation slope of -40dB/decade, introduces 180 of phase shift at frequencies above the LC resonant frequency. This phase shift, in addition to the inherent 180 of phase shift of the regulator's self-governing (negative) feedback system, poses the potential for positive feedback. The error amplifier and its associated circuitry are designed to compensate for this instability to achieve a stable closed-loop system. The basic regulator loop consists of a power modulator (comprised of the regulator's pulse-width modulator, associated circuitry, and LC filter), an output feedback divider, and an error amplifier. The power modulator has a DC gain set by VIN/VRAMP, where VRAMP's amplitude is typically 2VP-P. The output filter is effectively modeled as a double pole and a single zero set by the output inductance (L), the output capacitance (COUT), the DC resistance of the inductor (DCR), and its equivalent series resistance (ESR).
where ICL(MAX) is the maximum current limit. Figure 4 illustrates the effect of the MAX15002 ILIM reference current temperature coefficient to compensate for the variation of the MOSFET RDS(ON) over the operating junction temperature range.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate charge, RDS(ON), power dissipation, the maximum drainto-source voltage and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs that are optimized for high-frequency switching applications. The average gatedrive current from the MAX15002's output is proportional to the frequency and gate charge required to drive the MOSFET. The power dissipated in the MAX15002 is proportional to the input voltage and the average drive current (see the Power Dissipation section).
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Dual-Output Buck Controller with Tracking/Sequencing
Below are equations that define the power modulator: GMOD(DC) = fLC =
1 R +ESR 2 L x COUT x OUT ROUT +DCR VIN V = IN VRAMP 2V 1 2 L x COUT
First, select the passive and active power components that meet the application's output ripple, component size, and component cost requirements. Second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below.
MAX15002
fESR =
1 2 xESRx COUT
The switching frequency is programmable between 200kHz and 2.2MHz using an external resistor at RT. Typically, the crossover frequency (fCO), which is the frequency when the system's closed-loop gain is equal to unity (crosses the 0dB axis)--should be set at or below one-tenth the switching frequency (fSW/10) for stable, closed-loop response. The MAX15002 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use aluminum electrolytic capacitors and for space-sensitive applications, use low-ESR tantalum or multilayer ceramic chip (MLCC) capacitors at the output. The higher switching frequencies of the MAX15002 allow the use of MLCC as the primary filter capacitor(s).
Closed-Loop Response and Compensation of Voltage-Mode Regulators The power modulator's LC lowpass filter exhibits a variety of responses, depending on the value of the L and C (and their parasitics). One such response is shown in Figure 5a. In this example, the power modulator's uncompensated crossover is approximately 1/6th the desired crossover frequency, fCO. Note also, the uncompensated roll-off through the 0dB plane follows the double-pole, -40dB/dec slope and approaches 180 of phase shift, indicative of a potentially unstable system. Together with the inherent 180 of phase delay in the negative feedback system, this can lead to near 360 or positive feedback--an unstable system. The desired (compensated) roll-off follows a -20dB/dec slope (and commensurate 90 of phase shift), and, in this example, occurs at approximately 6x the uncompensated crossover frequency, fCO. In this example, a Type II compensator provides for stable closed-loop operation, leveraging the +20dB/dec slope of the capacitor's ESR zero (see Figure 5b).
POWER MODULATOR GAIN AND PHASE RESPONSE WITH LOSSY BULK OUTPUT CAPACITORS (ALUMINUM ELECTROLYTICS)
40 20 MAGNITUDE (dB) 0 -20 -40 -60 -80 10 100 1k 10k 100k 1M FREQUENCY (Hz) |GMOD| ASYMPTOTE < GMOD |GMOD| PHASE (DEGREES)
MAX15002 fig05a
POWER MODULATOR AND TYPE II COMPENSATOR GAIN AND PHASE RESPONSE WITH LOSSY BULK OUTPUT CAPACITORS (ALUMINUM ELECTROLYTICS)
80 60 40 MAGNITUDE (dB) MAX15002 fig05b
fLC
90 45 0
180 135 90 45 0 PHASE (DEGREES)
20 0 -20 -40
fESR
-45 -90 -135 -180 10M
< GMOD
fESR
-45 -90 |GMOD| -135 -180 10M
-60 -80 10 100 1k 10k 100k
1M
FREQUENCY (Hz)
Figure 5a. Power Modulator Gain and Phase Response (Large, Bulk COUT)
Figure 5b. Power Modulator (Large, Bulk COUT) and Type II Compensator Responses
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Dual-Output Buck Controller with Tracking/Sequencing
The Type II compensator's mid-frequency gain (approximately 4dB shown here) is designed to compensate for the power modulator's attenuation at the desired crossover frequency, fCO (GE/A + GMOD = 0dB at fCO). In this example, the power modulator's inherent -20dB/decade roll-off above the ESR zero (f ESR ) is leveraged to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5b, the net result is a 2x increase in the regulator's gain bandwidth while providing greater than 55 of phase margin (the difference between G E/A and G MOD respective phases at crossover, fCO). Other filter schemes pose their own problems. For instance, when choosing high-quality filter capacitor(s), e.g., MLCCs, and inductor, with minimal parasitics, the inherent ESR zero can occur at a much higher frequency, as shown in Figure 5c. As with the previous example, the actual gain and phase response is overlaid on the power modulator's asymptotic gain response. One readily observes the more dramatic gain and phase transition at or near the power modulator's resonant frequency, fLC, versus the gentler response of the previous example. This is due to the component's lower parasitics (OCR and ESR) and corresponding higher frequency of the inherent ESR
MAX15002
zero frequency. In this example, the desired crossover frequency occurs below the ESR zero frequency. In this example, a compensator with an inherent midfrequency double-zero response is required to mitigate the effects of the filter's double-pole. Such is available with the Type III topology. As demonstrated in Figure 5d, the Type III's mid-frequency double-zero gain (exhibiting a +20dB/dec slope, noting the compensator's pole at the origin) is designed to compensate for the power modulator's double-pole -40dB/decade attenuation at the desired crossover frequency, fCO (again, GE/A + GMOD = 0dB at fCO). See Figure 5d. In the above example, the power modulator's inherent (mid-frequency) -40dB/decade roll-off is mitigated by the mid-frequency double zero's +20dB/decade gain to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5d, the net result is an approximate doubling in the regulator's gain bandwidth while providing greater than 60 of phase margin (the difference between GE/A and GMOD respective phases at crossover, fCO). Design procedures for both Type II and Type III compensators are shown below.
POWER MODULATOR GAIN AND PHASE RESPONSE WITH LOW-PARASITIC OUTPUT CAPACITORS (MLCCs)
40 20 MAGNITUDE (dB) 0 -20 < GMOD -40 -60 -80 10 100 |GMOD| ASYMPTOTE 1k 10k 100k 1M |GMOD|
MAX15002 fig05c
POWER MODULATOR AND TYPE III COMPENSATOR GAIN AND PHASE RESPONSE WITH LOW PARASITIC OUTPUT CAPACITORS (MLCCs)
90 45 PHASE (DEGREES) 80 60 40 |GEA| < GEA fLC
MAX15002 fig05d
270 203 135 68 PHASE (DEGREES)
fLC fESR
MAGNITUDE (dB)
0 -45 -90 -135
20 0 -20 -40 -60 fESR 10 100 1k 10k 100k 1M < GMOD fCO |GMOD|
0 -68 -135 -203 -270 10M
-180 10M
-80 FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5c. Power Modulator Gain and Phase Response (HighQuality COUT)
Figure 5d. Power Modulator (High-Quality COUT) and Type III Compensator Responses
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Dual-Output Buck Controller with Tracking/Sequencing
Type II: Compensation When fCO > fESR
VOUT R1 FB VREF gM
1) Calculate the fZERO,ESR and LC double pole, fLC: fESR = fLC =
1 2 xESRx COUT 1 2 x L x COUT
MAX15002
COMP RF CF CCF
2) Calculate the unity-gain crossover frequency as:
f fCO SW 10
R2
+
3) Determine RF from the following:
V (2 x fCO xL)VOUT RF = RAMP VOUT x VIN x gm xESR
Figure 6a. Type II Compensation Network
GAIN (dB)
Note: RF is derived by setting the total loop gain at crossover frequency to unity, e.g., GEA(fCO) x GM(fCO) = 1V/V. The transconductance error amplifier gain is GEA(fCO) = gM x RF while the modulator gain is: GMOD (fCO ) =
VIN V ESR x x FB VRAMP 2 x fCO xL VOUT
1ST ASYMPTOTE GMODVREFVOUT-1(CF)-1 3RD ASYMPTOTE GMODVREFVOUT-1(CCF)-1
The total loop gain can be expressed logarithmically as follows:
20log10 gmRF +
[
]
2ND ASYMPTOTE GMODVREFVOUT-1RF
ESRx VIN x VFB = 0 dB 20log10 (2 x fCO xL ) x VOUT x VRAMP
(rad/sec)
1ST POLE (AT ORIGIN)
1ST ZERO RFCF
2ND POLE RFCCF
where V RAMP is the peak-to-peak ramp amplitude equal to 2V. 4) Place a zero at or below the LC double pole, fLC: CF =
1 2 xRF x fLC
Figure 6b. Type II Compensation Network Response
When the fCO is greater than fESR, a Type II compensation network provides the necessary closed-loop response. The Type II compensation network provides a midband compensating zero and high-frequency pole (see Figures 6a and 6b). R F C F provides the midband zero f MID,ZERO , and RFCCF provides the high-frequency pole fHIGH,POLE. Use the following procedure to calculate the compensation network components.
5) Place a high-frequency pole at or below fP = 0.5 x fSW: CCF =
1 xRF x fSW
6) Choose an appropriately sized R1 (connected from OUT_ to FB_, start with a 10k). Once R1 is selected, calculate R2 using the following equation:
FB R2 = R1 x VOUT - VFB V
where VFB = 0.6V.
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Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Type III: Compensation when fCO < fESR As indicated above, the position of the output capacitor's inherent ESR zero is critical in designing an appropriate compensation network. When low-ESR ceramic output capacitors are used, the ESR zero frequency (fESR) is usually much higher than unity crossover frequency (fCO). In this case, a Type III compensation network is recommended (see Figure 7a).
VOUT CCF RI CI R1 FB R2 RF CF
Two midband zeros (fZ1 and fZ2) are designed to cancel the pair of complex poles introduced by the LC filter. fP1 = at the origin (0Hz) fP1 introduces a pole at zero frequency (integrator) for nulling DC output-voltage errors. fP2 = 1 2 x RI x CI
Depending on the location of the ESR zero (fESR), fP2 can be used to cancel it, or to provide additional attenuation of the high-frequency output ripple. fP3 = 1 1 = 2 x RF x (CF || CCF ) 2 x R x CF x CCF F CF + CCF
gM +
COMP
VREF
Figure 7a. Type III Compensation Network
GAIN (dB)
fP3 attenuates the high-frequency output ripple. The locations of the zeros and poles should be such that the phase margin peaks around fCO. Set the ratios of fCO-to-fZ and fP-to-fCO equal to one another, e.g., fCO = fP = 5 is a good number to get about fZ fCO 60 of phase margin at fCO. Whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. The following procedure is recommended: 1) Select a crossover frequency, fCO, at or below onetenth the switching frequency:
f fCO SW 10
3RD POLE (rad/sec) RFCCF
4TH ASYMPTOTE RFRIC 3RD ASYMPTOTE RFCI 1ST ASYMPTOTE RICF-1 2ND ASYMPTOTE RFRI-1 1ST POLE (AT ORIGIN) 1ST ZERO 2ND POLE RFCF RICI 2ND ZERO RICI 5TH ASYMPTOTE RICCF-1
2) Calculate the LC double-pole frequency, fLC : fLC =
1 2x L x COUT
Figure 7b. Type III Compensation Network Response
As shown in Figure 7b, the Type III compensation network introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole at the origin, two zeros, and two higher frequency poles at the following frequencies: 1 fZ1 = 2 x RF x CF 1 fZ2 = 2 x CI x (R1 + RI)
3) Select RF 10k. 1 4) Place compensator's first zero fZ1 = 2 x RF x CF at or below the output filter's double pole, fLC, as follows: CF = 1 2 x RF x 0.5 x fLC
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Dual-Output Buck Controller with Tracking/Sequencing
5) The gain of the modulator (GainMOD)--comprised of the regulator's pulse-width modulator, LC filter, feedback divider, and associated circuitry--at crossover frequency is: GainMOD = 4 x 1 (2 x fCO ) x L x COUT
2
The gain of the error amplifier (GainE/A) in midband frequencies is: GainE/A = 2 x fCO x CI x RF The total loop gain as the product of the modulator gain and the error-amplifier gain at fCO should be equal to 1, as follows: GainMOD x GainE / A = 1 So : (2 x fCO ) x COUT x L SolvingforCI : CI = 4x 1
2
If a ceramic capacitor is used, the capacitor ESR zero, fESR, is likely to be located even above onehalf of the switching frequency, that is fLC < fCO < fSW/2 < fESR . In this case, the frequency of the second pole (fP2) should be placed high enough not to significantly erode the phase margin at the crossover frequency. For example, it can be set at 5 x fCO, so that its contribution to phase loss at the crossover frequency fCO is only about 11: fP2 = 5 x fCO Once fP2 is known, calculate RI: RI = 1 2 x fP2 x CI
MAX15002
7) Place the second zero (fZ2) at 0.2 x fCO or at fLC, whichever is lower and calculate R1 using the following equation: R1 = 1 2 x fZ2 x CI - RI
x 2 x fCO x CI x RF = 1
(2 x fCO x L x COUT )
4 x RF
8) Place the third pole (fP3) at 1/2 the switching frequency and calculate CCF from: CCF = 9) Calculate R2 as: R2 = R1 x where VFB = 0.6V. VFB VOUT - VFB 1 2 x 0.5 x fSW x RF
6) For those situations where f LC < f CO < f ESR < fSW/2--as with low-ESR tantalum capacitors--the compensator's second pole (fP2) should be used to cancel fESR. This provides additional phase margin. Viewed mathematically on the system Bode plot, the loop gain plot maintains its +20dB/decade slope up to 1/2 of the switching frequency verses flattening out soon after the 0dB crossover. Then set: fP2 = fESR
______________________________________________________________________________________
23
MAX15002
1.8V 44.2k 1.58k 10k 71.5k 46.4k 270F FOM58660 FOM58660 1H 100pF 2.7nF 11.0k 30.1k 680pF 22.1k
IN
LX2
BST2
DH2
DL2
CSP2
FB2
DREG2
CSN2
PGND2
COMP2
ILIM2
EN/TRACK2
(1/2)CMFSH-31
DREG1 (1/2) CMFSH-31 BST1 100nF EP LX1 CSN1 150F 200k 10k 1.91k 44.2k DL1 CSP1 560pF PGND1 EN1 FB1 2.7nF COMP1 49.1k 11.0k 47.6k FOM58660 DH1 FOM58690 1.4H 3.3V 47F
Dual-Output Buck Controller with Tracking/Sequencing
Figure 8. Coincident Dual Tracker with Lossless Current Sense
100nF 100nF 2.2
MAX15002
PGOOD2
SEL
PHASE
SYNC
RT
REG
SGND
CT
2.3F
499k
100nF
100k
RESET
24
100pF ILIM1 30.1k PGOOD1
IN
CIN
PGND
SGND
47F
2.2k
______________________________________________________________________________________
100F
Typical Operating Circuits
Dual-Output Buck Controller with Tracking/Sequencing
Typical Operating Circuits (continued)
VOUT1
MAX15002
PGOOD1 RESET CT SGND REG RT SYNC PHASE SEL
COMP1
DH1
DREG1
CSN1
PGND1
EP
VOUT2
IN
CIN
Figure 9. Dual Sequencer with Lossless Current Sense
______________________________________________________________________________________ 25
PGND
SGND
MAX15002
ILIM1
BST1
LX1
DL1
CSP1
EN1
FB1
EN/TRACK2
PGOOD2 COMP2 PGND2 DREG2 CSN2 ILIM2 CSP2 BST2 DH2 DL2 FB2 LX2 IN
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Typical Operating Circuits (continued)
VOUT1
ILIM1
PGOOD1 RESET CT SGND REG RT SYNC PHASE SEL
DREG1
DH1
DL1
CSN1
PGND1
EN1
EP
VOUT2
IN
CIN
Figure 10. Ratiometric Dual Tracker with Accurate Valley-Mode Current Sense
26 ______________________________________________________________________________________
PGND
AGND
MAX15002
COMP1
BST1
LX1
CSP1
FB1
EN/TRACK2
PGOOD2 COMP2 PGND2 DREG2 CSN2 ILIM2 CSP2 BST2 DH2 DL2 FB2 LX2 IN
Dual-Output Buck Controller with Tracking/Sequencing
PWM Controller Applications Information
Power Dissipation
The 40-pin TQFN thermally enhanced package can dissipate up to 2.96W. Calculate power dissipation in the MAX15002 as a product of the input voltage and the total REG output current (IREG). IREG includes quiescent current (I Q ) and the total gate drive current (IDREG): PD = VIN x IREG IREG = IQ + [fSW x (QG1 + QG2 + QG3 + QG4)] where QG1 to QG4 are the total gate charge of the lowside and high-side external MOSFETs. f SW is the switching frequency of the converter and IQ is the quiescent current of the device at the switching frequency. Use the following equation to calculate the maximum power dissipation (PDMAX) in the chip at a given ambient temperature (TA): PDMAX = 37 x (150 - TA)..........mW 3) Keep the current loop formed by the lower switching MOSFET, inductor and output capacitor short. 4) Keep SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) Run the current-sense lines CS+ and CS- close to each other to minimize the loop area. 6) Avoid long traces between the REG/DREG_ bypass capacitors, driver output of the MAX15002, MOSFET gates, and PGND. Minimize the loop formed by the REG_ bypass capacitors, bootstrap diode, bootstrap capacitor, high-side driver output of the MAX15002, and upper MOSFET gates. 7) Place the bank of output capacitors close to the load. 8) Distribute the power components evenly across the board for proper heat dissipation. 9) Provide enough copper area at and around the switching MOSFETs, and inductor to aid in thermal dissipation. 10) Connect the MAX15002 exposed paddle to a large copper plane to maximize its power dissipation capability. Connect the exposed paddle to SGND. Do not connect the exposed paddle to the SGND pin (pin 35) directly underneath the IC. 11) Use 2oz copper to keep the trace inductance and resistance to a minimum. Thin copper PCBs compromise efficiency because high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
MAX15002
PCB Layout Guidelines
Use the following guidelines to layout the switching voltage regulator. 1) Place the IN, REG, and DREG_ bypass capacitors close to the MAX15002. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal.
______________________________________________________________________________________
27
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Pin Configuration
PROCESS: BiCMOS
TOP VIEW
EN/TRACK2 PGOOD2 COMP2 CSN2 ILIM2 CSP2 N.C. N.C. BST2
Chip Information
30 29 28 27 26 25 24 23 22 21 N.C. 31 N.C. 32 N.C. 33 SYNC 34 SGND 35 RT 36 PHASE 37 RESET 38 CT 39 IN 40 1 REG 2 SEL 3 PGND1 4 DL1 5 DREG1 6 LX1 7 DH1 8 BST1 9 CSN1 10 CSP1 20 DH2 19 LX2 18 DREG2 17 DL2 16 PGND2
FB2
MAX15002
15 PGOOD1 14 FB1
+
EP*
13 EN1 12 COMP1 11 ILIM1
THIN QFN (6mm x 6mm)
*EP = EXPOSED PAD.
28
______________________________________________________________________________________
Dual-Output Buck Controller with Tracking/Sequencing
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX15002
______________________________________________________________________________________
QFN THIN.EPS
29
Dual-Output Buck Controller with Tracking/Sequencing MAX15002
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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